The present invention relates to test logic included in an integrated circuit for testing the interconnections between integrated circuits once they have been assembled onto a printed circuit board or other substrate, for testing the integrated circuit itself, and for observing or modifying circuit activity during the component's normal operation. In particular, the present invention relates to improvements increasing operating speed of boundary-scan architecture.
A product is typically constructed from a collection of components that are mounted on a printed circuit board, each of these components having a plurality of pins that connect the component to the circuit board. An integrated circuit used in a board-level design will normally have an established test methodology for that component. Components could be tested on an automatic test equipment system or by using a self-test procedure embedded in the design.
Once the component has been assembled onto the printed circuit board, access to the normal connections of the assembled circuit is limited. Providing the test data to the component and retrieving test data from the component is therefore difficult after assembly. Normally, an in-circuit test is needed in order to test the component in the same manner as it is tested in isolation.
For allowing test facilities built into the component to be used or to apply pre-existing patterns, test data needs to be conveyed to or from the boundaries of the individual component so that it can be tested as if it was free standing. An accepted method for conveying test data is with a boundary-scan cell coupled with a test access bus.
The conventional boundary-scan technique uses a shift-register stage contained in a boundary-scan cell that is located adjacent each component pin so that signals at the component boundaries can be controlled and observed using scan testing principles. The boundary-scan technique is well-known and is the subject of IEEE Std 1149.1-1990, relating to the IEEE Standard Test Access Port and Boundary-Scan Architecture, Institute of Electrical and Electronics Enginers, (May 21, 1990).
In order to test the component, test instructions and associated test data are fed into the component by the boundary-scan cell and, subsequently, the results of the execution of such instructions are read out. All of the information (instructions, test data, and test results) is communicated in a serial format. Typically, the sequence of operations is controlled by a bus master, which can be either automatic test equipment (ATE) or a component that interfaces to a higher-level test bus as a part of a complete system maintenance architecture. Control is achieved through signals applied to the test mode select and test clock inputs of the various components connected to the bus master.
Following execution of the test instruction, the results of the test are examined by shifting the data out of the component using the boundary-scan cell. The boundary-scan cells are connected directly to the connection pins of the individual components so that the test signals into and out of the component pass through the boundary-scan cell.
In conventional designs, the boundary-scan cell also receives the normal functional output data of the component when the cell is connected to an output pin of the component and the component is in the normal operation mode. At this time, the boundary-scan cell is not in the test mode and merely passes through the output data from the component. Since both functional data and test data pass through the boundary-scan cell, conventional boundary-scan cell design includes a multiplexer that selects between: (1) the functional data that is output by the component in normal operation; and (2) the test data output by the component or shifted in by another boundary-scan cell when the component and the boundary-scan cell are in a test mode.
In the normal functional operation of the component, the last functional register stage of the component outputs the data at the rising edge of the component clock signal. The functional data signal must then traverse the multiplexer of the boundary-scan cell before being outputted as the output signal of the component. In normal functional operation of the component, the boundary-scan cell therefore adds an off-chip delay that is equivalent to the multiplexer delay. This added delay can make it impossible for a design implemented in a specific technology to meet signal arrival times, unless the boundary-scan circuitry is completely removed and replaced with other, more costly test methods.